Integraged Circuits Engineering
| Numbering Code |
U-ENG26 46113 LJ11 U-ENG26 46113 LJ72 |
Year/Term | 2022 ・ First semester | |
|---|---|---|---|---|
| Number of Credits | 2 | Course Type | Lecture | |
| Target Year | Target Student | |||
| Language | Japanese | Day/Period | Thu.4 | |
| Instructor name |
SATOU TAKASHI (Graduate School of Informatics Professor) HASHIMOTO MASANORI (Graduate School of Informatics Professor) AWANO HIROMITSU (Graduate School of Informatics Associate Professor) |
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| Outline and Purpose of the Course | This lecture explains design methodologies for CMOS LSI circuits. Both analog and digital circuits will be covered. | |||
| Course Goals | From this lecture, you can understand design flow of CMOS LSI circuits. | |||
| Schedule and Contents |
Following topics will be covered. By assessing the understanding of the students and adding explanations and tasks when necessary, we will spend the number of weeks listed in [ ]. (1) CMOS process and devices [2 weeks] Overview of CMOS process technology related to LSI circuit design will be explained. Structures, characteristics and modeling methods for MOS transistors, capacitors, inductors and interconnects will be also explained. (2) Analog circuit design [2 weeks] Architecture and behavior of basic analog circuits such as constant current source and current mirror amplifier will be explained. Design methods for op-amps will be explained. (3) Digital circuit design [4 weeks] Design methodologies for combinational and sequential circuits are explained. Hardware algorithms for alithmetic logic unit will be discussed. (4) Evaluation and optimization of digital circuits [2 weeks] Methodologies for evaluating and optimizing the power consumption and delay of circuits are explained. Test methods will be also explained. (5) Full custom layout design [2 weeks] Design rules and layout verification methods will be explained. Full-custom layout design methods for analog circuits and basic logic gates are explained. Design methodologies for ROM and RAM will be explained. (6) Chip level layout design [2 weeks] Layout design methods and chip-level assembly methods in a cell-based design flow will be explained. (7) Confirmation of understanding [1 week] The level of understanding will be confirmed. Feedback will be given if necessary. |
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| Evaluation Methods and Policy | The level of achievement toward the goal of this lecture will be examined by the results of reports. All reports are mandatory. | |||
| Course Requirements | Logic circuits, Computer engineering, Digital circuits, Embedded computer system | |||
| Study outside of Class (preparation and review) | All reports are mandatory. Practices provided in the lecture should be solved after the lecture. | |||
| Textbooks | Textbooks/References | Hand-outs will be provided. | ||
| References, etc. | CMOS VLSI Design: A Circuits and Systems Perspective, Waste and Harris, (Addison Wesley), ISBN:978-0321547743 | |||
| Related URL | ||||
