Numbering Code	G-INF06 63657 LJ11	Year/Term	2022 ・ First semester
Number of Credits	2	Course Type	Lecture
Target Year		Target Student
Language	Japanese	Day/Period	Wed.3
Instructor name	TAKAGI NAOFUMI (Graduate School of Informatics Professor)
Outline and Purpose of the Course	We first learn instruction-level parallelism in a single processor, and then, learn data-level parallelism, thread-level parallelism, request-level parallelism, etc., as well as various parallel computer architectures and domain-specific computer architectures.
Course Goals	・Understanding instruction-level parallelism in a single processor and its limitations ・Understanding data-level parallelism, as well as SIMD extension, GPUs and vector processors utilizing it ・Understanding thread-level parallelism, as well as parallel processors utilizing it ・Understanding warehouse-scale computers ・Understanding domain-specific computer architectures
Schedule and Contents	・Introduction　(1) ・Instruction-level parallelism and its limitations (5) ・Data-level parallelism (3) ・Thread-level parallelism (2) ・Warehouse-scale computers (1) ・Domain-specific computer architectures (2) ・Term-end examination (1) ・Feedback (1)
Evaluation Methods and Policy	Term-end examination (about 70%) and reports (about 30%)
Course Requirements	Students are expected to have some prior knowledge on computer architecture and compilers.
Study outside of Class (preparation and review)	・Students are required to prepare for each classroom based on the textboo k and given slides . ・Students are required to solve exercises given at each classroom and to submit the answers till the specified date before the next classroom.
Textbooks	Textbooks/References	Computer Architecture; A Quantitative Approach, Sixth Edition, J. L. Hennessy and D. A. Patterson, (Morgan Kaufmann), ISBN:978-0-12-811905-1
Related URL	http://www.lab3.kuis.kyoto-u.ac.jp/~ntakagi/pca.html